Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits
نویسنده
چکیده
Key building blocks ± simple ternary inverter, positive ternary inverter and negative ternary inverter have been designed for operation at a low voltage ± 1 V in 2 lm, n-well standard CMOS process and simulated in SPICE3 for use in the design of ternary logic circuits. The back-gate bias method has been used in conjunction with the width/ channel (W/L) ratio of MOSFETs to generate the desired dc voltage transfer characteristics and transition region adjustment around midway between high and low logic levels. Ó 2000 Elsevier Science Ltd. All rights reserved.
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